MH6502 - Decode Logic (Ep3)

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To PLD or not to PLD

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When I start something interesting, I tend to overdo it. I originally contemplated using standard gates for my glue logic. But then chose to go the EEPLD (Electrically Erasable Programmable Logic Device) route. Wow, was I ambitious? Not only I was to build the 6502 single-board computer from the ground up, but I had to also get to know PLDs up close and personal at the same time. Well, it turns out it's not all that hard, if you find the right tutorials on the web, and if you have a precise memory map defined. I had this really particular memory map planned. But for my second iteration of the SBC, I opted to go simply and work my way up.  The map, for now, is 32K ROM, 16K IO space, and 16K RAM. This will change in the future. And this is the beauty of PLDs, there is no need to rewire anything. It's just the software that needs changing. I chose the ATF22V10C, a G22V10 equivalent, because of it's many input and output options: 12 dedicated inputs, and 10 configurable input/o...
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